ECE 512 - Digital System Testing and Design for Testability

★ 3 (fi 6) (either term, 3-0-0) Production testing versus design verification of digital VLSI/ULSI systems. Economics of testing. Defect distributions, yield analysis, and minimum fault coverage requirements. Fault modelling, fault simulation, and automatic test pattern generation. Memory testing. Iddq current-based testing. Design for testability (DFT) rules and strategies. Scan chain based DFT. Built-in self-test (BIST) circuits and architectures. The IEEE JTAG boundary scan and embedded core test standards. Advanced testing topics.